1. Technical Field of the Invention
The present invention relates to logic simulators used in the logic design of LSI circuitry, a logic simulation method for simulating operations of logic circuits, and a medium on which is recorded a program for simulating operations of logic circuits.
2. Background Art
In the development of LSI circuits, previously developed LSI logic circuits are often reused to further develop newer LSI circuits. FIGS. 4 and 5 show an example thereof. First, the LSI circuit shown in FIG. 4 is composed of a logic circuit A provided with functional macros A1.about.A4 having predetermined functions. The LSI circuit shown in FIG. 5 uses the LSI circuit of FIG. 4 as is, while including logic circuits B, C and D in addition to logic circuit A.
Developing LSI circuits by reusing previously developed logic circuits in this manner is an extremely effective means of reducing development costs. For example, in order to make an LSI circuit, a mask is necessary in order to form the elements and wiring comprising the logic circuit on a semiconductor wafer. Therefore, a mask pattern must be designed in order to obtain a mask for the development of each new LSI circuit. However, when a plurality of LSI circuits contain the same logic circuit A as in the above example and are made by the same production process, the same mask pattern can be used for the identical logic circuits A, or the mask pattern can be used by shrinking in response to an increase in the scale of the circuit. Therefore, when the LSI circuit shown in FIG. 4 is developed before the LSI circuit in FIG. 5 is developed, then it is possible to eliminate the development steps required for logic circuit A. Additionally, reusing previously developed logic circuits in this way is an effective means to use when mask pattern data cannot be reused because a plurality of LSI circuits have been made by different production processes. This is because the previously developed logic circuits have already been confirmed to be capable of functioning correctly when first lain on an LSI circuit, so that logic tests are not required on the finer portions of the new LSI circuits in the development stage.
As mentioned above, when LSI circuits have a common logic circuit, the number of development steps for each LSI circuit can be reduced by reusing the design data for that portion. However, in logic simulations performed during the logic design stage, the propriety of the logic functions in each LSI circuit overall must be tested, so that even if the LSI circuits have common logic circuits, logic simulations are duplicated on that portion as well. For this reason, duplicate calculations which are not actually necessary must be performed, as a result of which the amount of time required for the simulation increases. This can be explained in further detail as follows.
First, when a logic simulation is run on the LSI circuit shown in FIG. 4, the designer creates a net list corresponding to the logic circuit A and an input test vector which specifies the input signal waveforms to be applied to the logic circuit A. Here, the net list is data defining the structure of the logic circuit which is to be simulated. In the case of the example shown in FIG. 4, it is composed of data indicating that logic circuit A contains functional macros A1.about.A4, and that each functional macro is connected as shown in the drawing. Then, the net list and the input test vector are applied to the logic simulator, and the logic simulation of logic circuit A is run. In this logic simulation, the changes in the signal values (events) occurring at each node within the circuit due to the introduction of the input test vectors to the logic circuit A is sequentially calculated, and the output test vector finally outputted from the output terminals in the logic circuit A is determined. The designer decides whether or not the logic functions of the logic circuit A are proper based on this output test vector.
Next, performing a logic simulation of the LSI circuit shown in FIG. 5, the designer prepares a net list corresponding to the logic circuits to be lain on this LSI circuit, and an input test vector corresponding to the logic circuits. In the net list, it is possible to reuse that which was made in the development of the LSI circuit of FIG. 4 for the portion corresponding to logic circuit A. Then, the net list and input test vector are applied to the logic simulator, and the logic simulation is run. In this logic simulation, the logical function of the LSI circuit overall must be tested, so that the simulation is run with the logic circuit A operating. Therefore, the logic simulator must perform calculations on the events in the nodes within logic circuit A, so that the time required to perform the simulation becomes longer due to these calculations.
As explained above, when developing LSI circuits using previously developed logic circuits, there is conventionally a problem in that calculations must be duplicated even if the propriety of the logic circuits has been confirmed, so that the simulation is unnecessarily prolonged.